Continuous Optimization and Coordinated Power Management

As computer chip designers have pushed aggressively for higher performance processes, circuits, and systems, design margins have shrunk dramatically. For example, in the relatively recent past, peak power consumption was well below packaging limits for high-performance systems. However, today’s package limitations on both power consumption and heat dissipation have risen to first order design constraints. While most chips are designed for a particular maximum thermal operating point, they typically either operate far from that point or are throttled in a coarse grain fashion to prevent thermal violations. A typical workload for a computer system and how the workload uses the system components changes drastically over time. Web and e-commerce servers see varying load depending on the time of day. The ambient temperature seen by a computer in a machine room may vary not just on load, but also when other systems are added to or removed from the room. Applications with large data sets and irregular access patterns often exhibit poor cache behavior, leaving the processor stalled for extended periods of time, while other applications may be more processor or disk intensive. Even a single application goes through phases which place varying burdens on the system [1]. A system designed for maximum activity rates of all its components would certainly not exceed its power limits, but would typically operate far from its true capabilities. The key challenge is not solely to reduce power consumption, but instead to deliver energy to where it is most useful in the system at any given time. We propose to use on-line continuous optimization to dynamically tune the system to meet power, temperature, and energy constraints. While substantial opportunities for reducing power consumption are available, extending the current strategy of localized control of individual power management techniques is not viable. Without coordinated control, a collection of individual techniques may be enabled in destructive or ineffective combinations. Existing open-loop control techniques do not guarantee effective operation throughout the wide range of process variability, application space, and operating conditions. A simple reactive approach of enabling a power (or other metric) saving technique based on a pre-defined set of events such as ”after 1000 cycles of inactivity, transition to sleep mode” does not take into account the effectiveness of the action at runtime. Techniques that are applied globally, such as Intel’s recently announced ”Demand Based Switching” which allows fine grain adjustments to chip-wide voltage and frequency, lack the ability to channel the energy to different parts of the chip at different times. We propose to examine and evaluate closed-loop power management mechanisms that monitor and measure their effectiveness over time and across applications, as well as allocate energy to the most critical resources at any given time.